Contents
8255 Command word written in control register
BSR of 8255 – written into control register
8253/8254 Control Register Format
8254 Read Back Command – written into control register
8259 Initialization Command Words
8259 – Operation Command Words
8255
Port Address Map
|
Address |
Registers |
|
|
A1 |
A0 |
|
|
0 |
0 |
Port A |
|
0 |
1 |
Port B |
|
1 |
0 |
Port C |
|
1 |
1 |
Control Register/ BSR |
8255 Command word written in control register
|
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
|
1 Command Word is written to 8255 |
Mode of Port A 00 – mode0 (Simple I/O) 01 – mode 1 1X – mode 2 |
Port A 0 – o/p 1 – i/p |
Upper Port C 0 – o/p 1 – i/p |
Mode of Port B 0 – Mode0 Mode1 |
Port A 0 – o/p 1 – i/p |
Lower Port C 0 – o/p 1 – i/p |
|
BSR of 8255 – written into control register
|
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
|
0 BSR |
0 |
0 |
0 |
Port C Pin 000 – PC0 001 – PC1 010 – PC2 011 – PC3 100 – PC4 101 – PC5 110 – PC6 111 – PC& |
0 – Reset Bit 1 – Set Bit |
||
8254
Port Address Map
|
Address |
Registers |
|
|
A1 |
A0 |
|
|
0 |
0 |
Timer 0 |
|
0 |
1 |
Timer 1 |
|
1 |
0 |
Timer 2 |
|
1 |
1 |
Control Register |
8253/8254 Control Register Format
8254 Read Back Command – written into control register
|
Count – 0 – Read Count Status – 0 – Read Status |
|
C2 - 1 - Read from Timer2 C1 - 1 – Read from Timer 1 C0 – 1 – Read From Timer 0 |
8259
Programming Order
You can give OCW1 at this point to unmask individual interrupt request.
OCW2 is usually given at the end of the ISR
8259 Registers
8259 Initialization Command Words
Columns marked in yellow – not used for 8259
M/S – 1 for Master – 0 for Slave in a Cascaded 8259 System
SFNM & BUF – can be normally placed at zero
8259 – ICW 3 for Master Slave
In the master If Slave is connected to IR3 – S 3 made 1
In the slave ID2 ID1 ID0 will be 011
8259 – Operation Command Words
OCW1 is used masking individual interrupt requests – if IR1 IR2 IR3 are to be masked M3M2M1 are made 1
If SL = 1 L2L1L0 will have the Value of the Level.
16550- UART
Port Address Map
|
A2 |
A1 |
A0 |
Function |
|
0 |
0 |
0 |
RXB/TXB / BR – LSB When DL in Line Control Register - 0 During RD operation – receiver buffer is accessed If WR operation – transmit buffer is accessed When DL-1 Baud rate LSB accessed |
|
0 |
0 |
1 |
Int Enable /BR-MSB When DL -0 Interrupt Enable Register Accessed When Dl -1 Baud Rate MSB accessed |
|
0 |
1 |
0 |
Int Identification/ FIFO Control During RD – Interrupt Identification Accessed During WR – FIFO Control Accessed |
|
0 |
1 |
1 |
Line Control |
|
1 |
0 |
0 |
Modem Control |
|
1 |
0 |
1 |
Line Status |
|
1 |
1 |
0 |
Modem Status |
|
1 |
1 |
1 |
Scratch |
Register Format
Line Control Register
Baud Rate
FIFO Control Register
FIFO
16 bytes of storage
User writes data in FIFO
Data received goes into –FIFO –user reads from FIFO