Lab Schedule
Tutorial Schedule
Quiz Schedule
Notice for Quiz-1
Date: 29/1/2016
Syllabus: Module 1,2,3
Format: Open Book - Laptop, Tablet, Mobile not allowed.
Venue: Seating arrangement available in link below
Tutorial -3
Tutorial 3 will be conducted from 4:00-6:00 pm on Thursday 4th of Feb
Contact Session on 9/2/2016
The contact session scheduled on 9/2/2016 8:00-9:00 AM will be conducted on 11/2/2016 (Thursday) from 5:00-6:00 pm. As Friday Timetable is to be followed on that day - 5:00-6:00 slot is already blocked for MPI course. Venue will be mailed to you separately.
Test 1- Notice
Date: 24/2/2016
Time: 10:30AM - 11:30 AM
Type: Open Book (Laptops, Tablets, Mobiles not allowed)
Syllabus : Module 1 to 5
What will be tested:
- Understanding of X 86
- Programming Model
- Addressing modes (16-bit and 32-bit)
- Instruction Set of 80x86
- Assembly Language Programming skills
- Stack & Stack Operations
- Buses of 8086
- How Instructions are executed in 8086 - in terms instruction and machine cycles
Solutions for Test1
Marks for Test1
Recheck for Test1
Design Project
- Only four students/batch
- Design project allocation will be done using random no. generation.
- Update the batch members in the google sheet in link below before 5:00pm 18th March
Link for entering batch numbers
- Project batches with design problem number
- Design problem specifications can be downloaded from the DESIGN page
- Mentors are assigned for individual design problems - they will clear all doubts regarding the design problems
Problem No. |
Mentor |
Room No. |
Email ID (@goa.bits-pilani.ac.in) |
Preferred Hours of Interaction |
1 -4 |
Sarang C. Dhongdi |
A425 |
sarang |
M,W,F (10:00-5:00pm) |
5-8 |
Vikas.V.Khairnar |
PhD Hall |
p2013409 |
T,W any time |
9-12 & 33 |
Abhishek Dilip Joshi |
PhD Hall |
p2013410 |
|
13-16 |
Saif Dilavar |
PhD Hall |
p2013008 |
|
17-20 |
Rajalekshmi Kishore |
PhD Hall |
p2012401 |
|
21-24 |
Meetha.V.Shenoy |
AEx5 |
Meetha |
Any day except T,W |
24-28 |
Bhushan Kadam |
PhD Hall |
p2013010 |
W,Th,F from12:00 pm |
29-32 |
K.R.Anupama |
New Lab |
anupkr |
After 5:00 on any day except Thursday |
Test 2
T2 - Marks & Mid-semester Grades
Solutions have been uploaded in page Test & Compre Solns - Goa
Marks for Test2 & Mid-semester Grades
Re-Checked Marks
Lab Compre Schedule
Lab Comprehensive Examinations will be conducted on 17th April (Sunday) 8:00 AM - 11:30 AM.
The first batch will be from 8:00 AM to 9:30 AM and the second batch will be from 10:00 AM - 11:30 AM.
Check the file below for your lab timing details. Also ensure that you report 15 Minutes before the beginning of the exam at the Computer Centre. Exam is Open book.
Batch 1
Batch 2
Design Assignment
Design Example
click on icon to download ppt file of design example done in class
Instructions for Submission of Design Assignment
The Following Documents will have to be submitted for the design projects
A pdf documents that has the following contents
- Design Specifications
- Assumptions made when implementing the design
- Components used (no imaginary components allowed – make sure you have a data sheet of the component you are using)
- The complete hardware circuit diagram
- Flow chart of the software
A DSN file of the Proteus implementation
The asm file that contains the program
Zip the folder and name it with your batch no. If your batch no.is B113 – then name of the zipped folder will be B113.zip
There will be only one submission per batch
Note:
· The final circuit diagram you will submit show everything from clock generator to sensors and actuator interface even though they may not be there in your Proteus simulation
· The Proteus simulation is valid only if the hardware is correct.
The link for uploading the design is in dropbox
Upload your zipped assignment in the correct sub folder if your design question is P1 then upload in folder P1. The dropbox link will be mailed to you.
Viva Schedule
A Note on Plagiarism & Fake Data
What constitutes Plagiarism ?
- Not Just copy & paste
- Stealing ideas and work (even if it is the instructor's) without citation
Fake Data
- Creating models, modules , hardware that does not exist.
Either of this will earn you a zero in the assignment
Tips for your Viva
click on image to download file
Pre-Compre Total & Grades
click on image to download file
Any discrepancy in pre-compre marks meet Mr.Abhishek Dilip Joshi only from 4:00pm -5:00pm today (2/5/16).
Do not mail IC or any instructors in this regard.
Comprehensive Examination Notice
Date: 6/5/2016
Time: 9:00 AM - 12:00 Noon
Type - Open Book
PART A - Open Book - Objective - Built-in
Recommended Time : 1 Hour
Any Material allowed - but laptops will not be allowed
PART B - Open Book - Design Based
Recommended Time: 2 Hours
Any Material allowed - laptops allowed
Final Marks
Final Marks - After Rechecks
- Even students who have not collected papers have been rechecked and re-totaled
- No further recheck requests will be entertained.
- You can only collect the papers from PhD Chambers (above library) from Mr.Vikas Khairnar